The radiological image sensor normally comprises a semiconductor chip having a matrix of photosensitive members and linked electronic circuits, a printed circuit board on which the chip and possibly some other components are mounted, a scintallator covering the chip, and occasionally a fiber-optic plate inserted between the scintillator and the chip. The unit is contained in a resin package B (FIG. 1) from which a connection cable C may extend to a system for processing the collected images (except in the case of wireless transmission, in which case a battery is provided, as a rule, in the package). The package conforms as closely as possible to the shape of the chip so as not to create unnecessary bulk.
The shape of the chip which is, a priori, rectangular requires the package to have a rectangular shape, which is neither ergonomic nor comfortable for the patient.
To improve the ergonomics and comfort in radiological image sensors which are made using CCD (“Charge Coupled Devices”) technology, it has already been proposed to cut the corners of the package or make them round. To prevent losing image capture surface, it has been proposed in this case to use a chip which itself has cut corners. Sensors with chips having two cut corners (the two corners located at the front in the direction in which the sensor is inserted into the mouth) have been proposed (FIG. 1); sensors with four cut corners have also been proposed (FIG. 2). This results in structure adjustments such as, for example, the installation of a charge reading register in the middle of the chip rather than on the edges. These adjustments are possible in CCD technologies. They are not possible in CMOS technologies, i.e. technologies in which the photosensitive members have active members made from MOS transistors at each pixel in order to convert the photogenerated charges into voltage or current, and in which the current or voltage signals corresponding to each pixel are transmitted on a column conductor linked with each column of pixels.
Indeed, these technologies do not use a charge transfer register and reading systems could not be placed right in the middle of the chip without neutralizing an extremely large image area, and this is not acceptable.
However, CMOS technologies are extremely beneficial since they allow easy production, on a single integrated circuit chip, of both an image acquisition matrix and linked electronic circuits (control circuits, image signal collection circuits, image processing circuits, etc.). Moreover, these are technologies that consume less energy, which is advantageous.
This is why there is a need to combine the advantages of CMOS technology and the ergonomic shape of chips having cut corners.
There is however one considerable difficulty in carrying out this combination. This difficulty can be seen by referring first to FIG. 3 which schematically depicts a rectangular image sensor chip. The majority of the surface is taken up by a matrix 10 of lines and columns of photosensitive active members.
In practice, the matrix includes, for each line of pixels, one or more line conductors connecting all of the pixels of a same line, and for each column of pixels, a column conductor connecting all of the pixels of one and the same column.
The operation of such a CMOS technology matrix requires                a line select circuit, 20, to successively designate each line during an image reading operation; this is a purely digital circuit; it includes a line select block opposite each line;        a read circuit 30 for reading currents or voltages present on the column conductors during the addressing of a determined line, including, in principle, a circuit for storing these voltages or currents in order to store the image signals corresponding to the addressed line for the duration of the individual reading of all of the stored signals corresponding to this line; the signals which are coming from the pixels of this line and which are stored are indeed read sequentially on an output conductor of the matrix (not shown) to which the various current or voltage read blocks of the circuit 30 (one block per column) are connected; the read circuit 30 is a hybrid analog/digital circuit;        a column select circuit 40 for successively designating each column during an operation for reading a line that has just been stored; the designation of a column allows the stored signal corresponding to this column to be transmitted to the output of the matrix; the column select circuit is a digital circuit; it includes a select block linked with each read block, and therefore linked with each column; this circuit 40 is not necessarily present, in particular when the image sensor comprises a high-speed analog-to-digital converter at the output of the read circuit 30;        various electronic circuits and input/output pads of the chip, the assembly being housed in a space given the general reference 50; these circuits can notably include a sequencer for the successive addressing of the lines and then the columns for a given line.        
The read and select circuits are placed at the periphery of the matrix, opposite the lines on the one hand, and the columns on the other. The line select circuit 20 extends along a vertical edge of the matrix, parallel to the columns, with a block opposite each line; it can be split and can extend along the two vertical edges. The reading (and storage) circuit 30 extends, for example, along the horizontal lower edge of the matrix. The column select circuit 40 also extends along the horizontal lower edge, below the read circuit 30. The space 50 extends below the circuit 40. More precisely, the line select circuit 20 includes a multi-conductor address bus (not shown) which extends along the entirety of a vertical edge of the matrix, parallel to the columns, and a select block opposite each line. The inputs of the select block are the bus conductors and the outputs are one or more line conductors which horizontally connect all of the pixels of the line corresponding to the elementary block.
The storage and current or voltage read circuit 30 includes, for each column, an elementary read block which carries out the reading and storage function; this block is positioned opposite this column, and it receives, as an input, the column conductor corresponding to this column. This block can comprise a buffer amplifier, one or more associated capacitors, and switches; it acts as a sample-and-hold circuit, i.e. in a first phase it samples a current or voltage value present on the column conductor, and in a second phase, it stores the sampled voltage until its content is read (sequential reading, block by block).
The column select circuit 40 includes an address bus (not shown) formed of several conductors, which extends along a horizontal edge of the matrix, parallel to the lines, and a column select block opposite each column; this select block is a decoding circuit (but could be a simple shift register) whose inputs are the conductors of this address bus and whose output is a signal for controlling a switch inserted between the current or voltage read block linked with the corresponding column and the output conductor of the matrix. The address bus selects an elementary block and connects, to the output conductor, the output of the sample-and-hold circuit linked with the designated column. The output conductor successively provides the image signals corresponding to each pixel of the matrix, line by line and pixel by pixel in the line.
Thus, for a line addressed by the line address bus, the signals of all of the pixels of the line are stored in the read blocks 30 located at the bottom of the matrix, then they are successively transmitted to the output under the control of the column address bus, before a new line is addressed.
If a matrix with two or four cut corners is now used instead of the rectangular matrix of FIG. 3, the line select circuit extends partially along the oblique edges making up the bevels of the matrix in order to remain opposite each line of the matrix while being housed in the narrow residual space between the edge of the matrix and the edge of the chip. This, in itself, does not cause a particular problem. FIG. 4 shows the general arrangement for a matrix with two cut corners.
However, in the case of a matrix with four cut corners, the column select circuit and the current or voltage read circuit must also extend partially along the cut corners in order to remain opposite the columns that terminate on these corners. It has been noted that this arrangement can generate a fixed pattern noise (FPN). Indeed, the nonuniform position and production of analog circuits creates small gain differences which are found in the image in the form of fixed pattern noise: the individual read circuits should all be absolutely identical, but they are not in reality. There is a factor of dependence between the gain of an amplifier for example and the position of the amplifier in the chip. In the case where amplifiers are located on a single line, it is quite easy to correct the effect of this dependence along a geometrical axis. In the case where they are located both on a horizontal line (dependence along one axis) and on an oblique line (dependence along two axes), this correction is a lot more difficult and there is a risk that fixed noise linked to the structure (and not only to technological imperfections) will remain in spite of the corrections.
Moreover, on the oblique corners of the matrix, it is not possible to have, as is the case with a rectangular matrix, the line select blocks along a horizontal edge and the read blocks along a vertical edge. The two series are placed along one and the same oblique edge. A choice must therefore be made as to whether to position the line select blocks in immediate proximity to the lines or the read blocks in immediate proximity to the columns, but it is not possible have both at the same time. Yet, in both cases, this requires line address signals to be passed above the read blocks. These signals are digital signals of large amplitude which exert a virtually unacceptable capacitive effect on the read blocks which are extremely sensitive to capacitive effects (these are analog circuits for measuring extremely small currents and voltages). It would therefore be necessary to insert shielding layers between the lines transporting digital signals and the read blocks; this is difficult to do given the limited number of conductive levels available at the location of the read blocks (these blocks, in principle, use all of the conductive levels that the technology used makes available).
FIGS. 5 and 6 show two examples of structures illustrating the possible positions of the select and read circuits in a matrix with four cut corners: line select blocks 20 in immediate proximity to the bevel of the matrix in FIG. 5, and current or voltage read blocks 30 in immediate proximity to the bevel in FIG. 6.
To solve the difficulties linked with these structures, the invention proposes an image sensor having a chip with cut corners, comprising a matrix of horizontal lines and vertical columns of photosensitive members, the matrix having a generally rectangular shape of horizontal width L and having four bevels, the sensor comprising as many current or voltage read blocks as there are matrix columns, in order to read the image signals detected by the photosensitive members of a column and transmitted by a column conductor linked with this column, characterized in that the current or voltage read blocks are placed along a horizontal edge of the matrix and are all housed within a vertical strip, the width L1 of which is substantially less than the maximum width L of the matrix.
In practice, if L′ is the width at the bottom of the matrix, i.e. the narrow horizontal width which remains between the bevels at the bottom of the matrix (on the side where the current or voltage read blocks are located), all of the blocks would be fitted into the width L′ or into a width which is more or less equal to the width L′.
If the sensor comprises column select blocks linked with the read blocks, these column select blocks would be all housed in the same width L1.